Changeset 2be477d5 in mainline for uspace/drv/bus/usb/ehci/ehci_regs.h
- Timestamp:
- 2014-01-19T06:26:14Z (10 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- bd41b192
- Parents:
- 4ee5272
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/bus/usb/ehci/ehci_regs.h
r4ee5272 r2be477d5 42 42 #define EHCI_RD(reg) uint32_t_le2host(pio_read_32(&(reg))) 43 43 #define EHCI_RD8(reg) pio_read_8(&(reg)) 44 //#define EHCI_SET(reg, val) reg |= host2uint32_t_le(val)45 //#define EHCI_CLR(reg, val) reg &= host2uint32_t_le(~val)44 #define EHCI_SET(reg, val) pio_set_32(&(reg), host2uint32_t_le(val), 0) 45 #define EHCI_CLR(reg, val) pio_clear_32(&(reg), host2uint32_t_le(val), 0) 46 46 47 47 /** EHCI memory mapped capability registers structure */ … … 135 135 #define USB_PORTSC_WKDSCNNT_E_FLAG (1 << 21) 136 136 #define USB_PORTSC_WKCNNT_E_FLAG (1 << 20) 137 #define USB_PORTSC_PORT_TEST_MASK 0xf 138 #define USB_PORTSC_PORT_TEST_SHIFT 16 139 #define USB_PORTSC_NO_TEST 0x0 140 #define USB_PORTSC_TEST_J_STATE 0x1 141 #define USB_PORTSC_TEST_K_STATE 0x2 142 #define USB_PORTSC_TEST_SE0_NAK 0x3 143 #define USB_PORTSC_TEST_PACKET 0x4 144 #define USB_PORTSC_TEST_FORCE_ENABLE 0x5 145 #define USB_PORTSC_INDICATOR_MASK 0x3 146 #define USB_PORTSC_INDICATOR_SHIFT 14 147 #define USB_PORTSC_INDICATOR_OFF 0x0 148 #define USB_PORTSC_INDICATOR_AMBER 0x1 149 #define USB_PORTSC_INDICATOR_GREEN 0x2 137 #define USB_PORTSC_PORT_TEST_MASK (0xf << 16) 138 #define USB_PORTSC_NO_TEST (0x0 << 16) 139 #define USB_PORTSC_TEST_J_STATE (0x1 << 16) 140 #define USB_PORTSC_TEST_K_STATE (0x2 << 16) 141 #define USB_PORTSC_TEST_SE0_NAK (0x3 << 16) 142 #define USB_PORTSC_TEST_PACKET (0x4 << 16) 143 #define USB_PORTSC_TEST_FORCE_ENABLE (0x5 << 16) 144 #define USB_PORTSC_INDICATOR_MASK (0x3 << 14) 145 #define USB_PORTSC_INDICATOR_OFF (0x0 << 14) 146 #define USB_PORTSC_INDICATOR_AMBER (0x1 << 14) 147 #define USB_PORTSC_INDICATOR_GREEN (0x2 << 14) 150 148 #define USB_PORTSC_PORT_OWNER_FLAG (1 << 13) 151 149 #define USB_PORTSC_PORT_POWER_FLAG (1 << 12) 152 #define USB_PORTSC_LINE_STATUS_MASK 0x3 153 #define USB_PORTSC_LINE_STATUS_SHIFT 10 154 #define USB_PORTSC_LINE_STATUS_SE0 0x0 155 #define USB_PORTSC_LINE_STATUS_K 0x1 156 #define USB_PORTSC_LINE_STATUS_J 0x2 150 #define USB_PORTSC_LINE_STATUS_MASK (0x3 << 10) 151 #define USB_PORTSC_LINE_STATUS_SE0 (0x0 << 10) 152 #define USB_PORTSC_LINE_STATUS_K (0x1 << 10) 153 #define USB_PORTSC_LINE_STATUS_J (0x2 << 10) 157 154 #define USB_PORTSC_PORT_RESET_FLAG (1 << 8) 158 155 #define USB_PORTSC_SUSPEND_FLAG (1 << 7) … … 164 161 #define USB_PORTSC_CONNECT_CH_FLAG (1 << 1) 165 162 #define USB_PORTSC_CONNECT_FLAG (1 << 0) 163 164 #define USB_PORTSC_WC_MASK \ 165 (USB_PORTSC_CONNECT_CH_FLAG | USB_PORTSC_EN_CHANGE_FLAG | USB_PORTSC_OC_CHANGE_FLAG) 166 166 } ehci_regs_t; 167 167
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