Changeset 2bcf6c6 in mainline for kernel/arch/amd64/include/atomic.h
- Timestamp:
- 2012-07-27T13:34:48Z (12 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 4ec9ea41
- Parents:
- 3bb732b
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/amd64/include/atomic.h
r3bb732b r2bcf6c6 140 140 } 141 141 142 143 #define _atomic_cas_ptr_impl(pptr, exp_val, new_val, old_val, prefix) 144 asm volatile ( \ 145 prefix " cmpxchgq %[newval], %[ptr]\n" \ 146 : /* Output operands. */ \ 147 /* Old/current value is returned in eax. */ \ 148 [oldval] "=a" (old_val), \ 149 /* (*ptr) will be read and written to, hence "+" */ \ 150 [ptr] "+m" (*pptr) \ 151 : /* Input operands. */ \ 152 /* Expected value must be in eax. */ \ 153 [expval] "a" (exp_val), \ 154 /* The new value may be in any register. */ \ 155 [newval] "r" (new_val) \ 156 : "memory" \ 157 ) 158 159 /** Atomically compares and swaps the pointer at pptr. */ 160 NO_TRACE static inline void * atomic_cas_ptr(void **pptr, 161 void *exp_val, void *new_val) 162 { 163 void *old_val; 164 _atomic_cas_ptr_impl(pptr, exp_val, new_val, old_val, "lock\n"); 165 return old_val; 166 } 167 168 /** Compare-and-swap of a pointer that is atomic wrt to local cpu's interrupts. 169 * 170 * This function is NOT smp safe and is not atomic with respect to other cpus. 171 */ 172 NO_TRACE static inline void * atomic_cas_ptr_local(void **pptr, 173 void *exp_val, void *new_val) 174 { 175 void *old_val; 176 _atomic_cas_ptr_impl(pptr, exp_val, new_val, old_val, ""); 177 return old_val; 178 } 179 180 #undef _atomic_cas_ptr_impl 181 182 142 183 #endif 143 184
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