Changeset 28f81d21 in mainline

Timestamp:

2012-11-24T11:24:35Z (11 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

04cb6957

Parents:

d238aa9

Message:

arm32, fpu context: Use register interval instead of listing every single one

File:

• kernel/arch/arm32/src/cpu/cpu.c (modified) (2 diffs)

kernel/arch/arm32/src/cpu/cpu.c

@@ -172 +172 @@
 //              "vmrs r2, fpexc\n"
                 "stm %0, {r1, r2}\n"
-                "vstm %0, {d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15}\n"
+                "vstm %0, {d0-d15}\n"
                 ::"r" (ctx): "r1","r2","memory"
         );
@@ -184 +184 @@
                 "vmsr fpscr, r1\n"
 //              "vmsr fpexc, r2\n"
-                "vldm %0, {d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15}\n"
+                "vldm %0, {d0-d15}\n"
                 ::"r" (ctx): "r1","r2"
         );