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Changeset 26e3db2 in mainline


Ignore:
Timestamp:
2013-01-19T18:50:56Z (9 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master
Children:
612edca
Parents:
a03b609
Message:

arm32: Switch cpu identification to cp15 helpers.

Location:
kernel/arch/arm32
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm32/include/cp15.h

    ra03b609 r26e3db2  
    5555
    5656/* Identification registers */
     57enum {
     58        MIDR_IMPLEMENTER_MASK = 0xff,
     59        MIDR_IMPLEMENTER_SHIFT = 24,
     60        MIDR_VARIANT_MASK = 0xf,
     61        MIDR_VARIANT_SHIFT = 20,
     62        MIDR_ARCHITECTURE_MASK = 0xf,
     63        MIDR_ARCHITECTURE_SHIFT = 16,
     64        MIDR_PART_NUMBER_MASK = 0xfff,
     65        MIDR_PART_NUMBER_SHIFT = 4,
     66        MIDR_REVISION_MASK = 0xf,
     67        MIDR_REVISION_SHIFT = 0,
     68};
    5769CONTROL_REG_GEN_READ(MIDR, c0, 0, c0, 0);
    5870CONTROL_REG_GEN_READ(CTR, c0, 0, c0, 1);
  • kernel/arch/arm32/src/cpu/cpu.c

    ra03b609 r26e3db2  
    9999static void arch_cpu_identify(cpu_arch_t *cpu)
    100100{
    101         uint32_t ident;
    102         asm volatile (
    103                 "mrc p15, 0, %[ident], c0, c0, 0\n"
    104                 : [ident] "=r" (ident)
    105         );
    106        
    107         cpu->imp_num = ident >> 24;
    108         cpu->variant_num = (ident << 8) >> 28;
    109         cpu->arch_num = (ident << 12) >> 28;
    110         cpu->prim_part_num = (ident << 16) >> 20;
    111         cpu->rev_num = (ident << 28) >> 28;
     101        const uint32_t ident = MIDR_read();
     102
     103        cpu->imp_num = (ident >> MIDR_IMPLEMENTER_SHIFT) & MIDR_IMPLEMENTER_MASK;
     104        cpu->variant_num = (ident >> MIDR_VARIANT_SHIFT) & MIDR_VARIANT_MASK;
     105        cpu->arch_num = (ident >> MIDR_ARCHITECTURE_SHIFT) & MIDR_ARCHITECTURE_MASK;
     106        cpu->prim_part_num = (ident >> MIDR_PART_NUMBER_SHIFT) & MIDR_PART_NUMBER_MASK;
     107        cpu->rev_num = (ident >> MIDR_REVISION_SHIFT) & MIDR_REVISION_MASK;
     108
    112109        // TODO CPUs with arch_num == 0xf use CPUID scheme for identification
    113110        cpu->dcache_levels = dcache_levels();
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