Changeset 1eb154f in mainline

Timestamp:

2008-06-15T11:07:37Z (16 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

3527a93

Parents:

c711efe

Message:

Don't make any assumptions about the contents of the I-cache in sparc64
loader and before passing control to the kernel, invalidate the I-cache.

Location:

boot/arch/sparc64/loader

Files:

• asm.S (modified) (2 diffs)
• ofwarch.c (modified) (3 diffs)

boot/arch/sparc64/loader/asm.S

@@ -100 +100 @@
 jump_to_kernel:
         /*
-         * Make sure that the code we have moved has drained to main memory.
-         * We have a reason to assume that the I-cache does not include the
-         * code to which we are going to pass control. Hence no I-cache
-         * invalidation.
+         * We have copied code and now we need to guarantee cache coherence.
+         * 1. Make sure that the code we have moved has drained to main memory.
+         * 2. Invalidate I-cache.
+         * 3. Flush instruction pipeline.
          */ 
-        membar #StoreStore
+        call    icache_flush
+        membar  #StoreStore
+        flush   %i7
 
         mov %o0, %l1
@@ -112 +114 @@
         mov %o3, %o2
         jmp %l1                         ! jump to kernel
+        nop
+
+#define ICACHE_SIZE             8192
+#define ICACHE_LINE_SIZE        32
+#define ICACHE_SET_BIT          (1 << 13)
+#define ASI_ICACHE_TAG          0x67
+
+# Flush I-cache
+icache_flush:
+        set     ((ICACHE_SIZE - ICACHE_LINE_SIZE) | ICACHE_SET_BIT), %g1
+        stxa    %g0, [%g1] ASI_ICACHE_TAG
+0:      membar  #Sync
+        subcc   %g1, ICACHE_LINE_SIZE, %g1
+        bnz,pt  %xcc, 0b
+        stxa    %g0, [%g1] ASI_ICACHE_TAG
+        membar  #Sync
+        retl
+        ! SF Erratum #51
         nop
 

boot/arch/sparc64/loader/ofwarch.c

@@ -70 +70 @@
         uint64_t current_mid;
         
-        asm volatile ("ldxa [%1] %2, %0\n" : "=r" (current_mid) : "r" (0), "i" (ASI_UPA_CONFIG));
+        asm volatile ("ldxa [%1] %2, %0\n"
+            : "=r" (current_mid)
+            : "r" (0), "i" (ASI_UPA_CONFIG));
         current_mid >>= UPA_CONFIG_MID_SHIFT;
         current_mid &= UPA_CONFIG_MID_MASK;
@@ -76 +78 @@
         int cpus;
         
-        for (cpus = 0; node != 0 && node != -1; node = ofw_get_peer_node(node), cpus++) {
-                if (ofw_get_property(node, "device_type", type_name, sizeof(type_name)) > 0) {
+        for (cpus = 0; node != 0 && node != -1; node = ofw_get_peer_node(node),
+            cpus++) {
+                if (ofw_get_property(node, "device_type", type_name,
+                    sizeof(type_name)) > 0) {
                         if (strcmp(type_name, "cpu") == 0) {
                                 uint32_t mid;
                                 
-                                if (ofw_get_property(node, "upa-portid", &mid, sizeof(mid)) <= 0)
+                                if (ofw_get_property(node, "upa-portid", &mid,
+                                    sizeof(mid)) <= 0)
                                         continue;
                                         
@@ -88 +93 @@
                                          * Start secondary processor.
                                          */
-                                        (void) ofw_call("SUNW,start-cpu", 3, 1, NULL, node,
-                                                 KERNEL_VIRTUAL_ADDRESS,
-                                                 bootinfo.physmem_start | AP_PROCESSOR);
+                                        (void) ofw_call("SUNW,start-cpu", 3, 1,
+                                            NULL, node, KERNEL_VIRTUAL_ADDRESS,
+                                            bootinfo.physmem_start |
+                                            AP_PROCESSOR);
                                 }
                         }