Changeset 1cdb412 in mainline for kernel/genarch/src/drivers/amdm37x_uart/amdm37x_uart.c

Timestamp:

2012-03-31T06:27:28Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

d01b9a1

Parents:

64f6cba8

Message:

mdm37x, uart: Fix initialziation, setup receive fifo.

Do not reset the port.

File:

• kernel/genarch/src/drivers/amdm37x_uart/amdm37x_uart.c (modified) (6 diffs)

kernel/genarch/src/drivers/amdm37x_uart/amdm37x_uart.c

@@ -72 +72 @@
 {
         amdm37x_uart_t *uart = irq->instance;
-//TODO enable while checking when RX FIFO is used instead of single char.
-//      while (!(uart->regs->isr2 & AMDM37x_UART_ISR2_RX_FIFO_EMPTY_FLAG)) {
+        while (!(uart->regs->isr2 & AMDM37x_UART_ISR2_RX_FIFO_EMPTY_FLAG)) {
                 const uint8_t val = uart->regs->rhr;
                 if (uart->indev && val) {
                         indev_push_character(uart->indev, val);
                 }
-//      }
+        }
 }
 
@@ -93 +92 @@
         /* Soft reset the port */
         uart->regs->sysc = AMDM37x_UART_SYSC_SOFTRESET_FLAG;
-        while (uart->regs->syss & AMDM37x_UART_SYSS_RESETDONE_FLAG) ;
+        while (!(uart->regs->syss & AMDM37x_UART_SYSS_RESETDONE_FLAG)) ;
+#endif
 
         /* Enable access to EFR register */
@@ -106 +106 @@
         /* Set default (val 0) triggers, disable DMA enable FIFOs */
         const bool tcl_tlr = uart->regs->mcr & AMDM37x_UART_MCR_TCR_TLR_FLAG;
+        /* Enable access to tcr and tlr registers */
+        uart->regs->mcr |= AMDM37x_UART_MCR_TCR_TLR_FLAG;
+
+        /* Enable FIFOs */
         uart->regs->fcr = AMDM37x_UART_FCR_FIFO_EN_FLAG;
 
-        /* Enable fine granularity for rx trigger */
+        /* Eneble fine granularity for RX FIFO and set trigger level to 1,
+         * TX FIFO, trigger level is irelevant*/
         uart->regs->lcr = 0xbf;              /* Sets config mode B */
         uart->regs->scr = AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG;
+        uart->regs->tlr = 1 << AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT;
 
         /* Restore enhanced */
@@ -117 +123 @@
 
         uart->regs->lcr = 0x80;              /* Config mode A */
-        /* Restore tcl_lcr */
+        /* Restore tcl_lcr access flag*/
         if (!tcl_tlr)
                 uart->regs->mcr &= ~AMDM37x_UART_MCR_TCR_TLR_FLAG;
 
-        /* Restore tcl_lcr */
+        /* Restore lcr */
         uart->regs->lcr = lcr;
 
         /* Disable interrupts */
         uart->regs->ier = 0;
-#endif
+
         /* Setup outdev */
         outdev_initialize("amdm37x_uart_dev", &uart->outdev, &amdm37x_uart_ops);
@@ -138 +144 @@
         uart->irq.handler = amdm37x_uart_handler;
         uart->irq.instance = uart;
-        irq_register(&uart->irq);
 
         return true;
@@ -148 +153 @@
         /* Set indev */
         uart->indev = indev;
+        /* Register interrupt. */
+        irq_register(&uart->irq);
         /* Enable interrupt on receive */
         uart->regs->ier |= AMDM37x_UART_IER_RHR_IRQ_FLAG;
-
-        // TODO set rx fifo
-        // TODO set rx fifo threshold to 1
 }