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Changeset 1cdb412 in mainline


Ignore:
Timestamp:
2012-03-31T06:27:28Z (10 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master
Children:
d01b9a1
Parents:
64f6cba8
Message:

mdm37x, uart: Fix initialziation, setup receive fifo.

Do not reset the port.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/genarch/src/drivers/amdm37x_uart/amdm37x_uart.c

    r64f6cba8 r1cdb412  
    7272{
    7373        amdm37x_uart_t *uart = irq->instance;
    74 //TODO enable while checking when RX FIFO is used instead of single char.
    75 //      while (!(uart->regs->isr2 & AMDM37x_UART_ISR2_RX_FIFO_EMPTY_FLAG)) {
     74        while (!(uart->regs->isr2 & AMDM37x_UART_ISR2_RX_FIFO_EMPTY_FLAG)) {
    7675                const uint8_t val = uart->regs->rhr;
    7776                if (uart->indev && val) {
    7877                        indev_push_character(uart->indev, val);
    7978                }
    80 //      }
     79        }
    8180}
    8281
     
    9392        /* Soft reset the port */
    9493        uart->regs->sysc = AMDM37x_UART_SYSC_SOFTRESET_FLAG;
    95         while (uart->regs->syss & AMDM37x_UART_SYSS_RESETDONE_FLAG) ;
     94        while (!(uart->regs->syss & AMDM37x_UART_SYSS_RESETDONE_FLAG)) ;
     95#endif
    9696
    9797        /* Enable access to EFR register */
     
    106106        /* Set default (val 0) triggers, disable DMA enable FIFOs */
    107107        const bool tcl_tlr = uart->regs->mcr & AMDM37x_UART_MCR_TCR_TLR_FLAG;
     108        /* Enable access to tcr and tlr registers */
     109        uart->regs->mcr |= AMDM37x_UART_MCR_TCR_TLR_FLAG;
     110
     111        /* Enable FIFOs */
    108112        uart->regs->fcr = AMDM37x_UART_FCR_FIFO_EN_FLAG;
    109113
    110         /* Enable fine granularity for rx trigger */
     114        /* Eneble fine granularity for RX FIFO and set trigger level to 1,
     115         * TX FIFO, trigger level is irelevant*/
    111116        uart->regs->lcr = 0xbf;              /* Sets config mode B */
    112117        uart->regs->scr = AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG;
     118        uart->regs->tlr = 1 << AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT;
    113119
    114120        /* Restore enhanced */
     
    117123
    118124        uart->regs->lcr = 0x80;              /* Config mode A */
    119         /* Restore tcl_lcr */
     125        /* Restore tcl_lcr access flag*/
    120126        if (!tcl_tlr)
    121127                uart->regs->mcr &= ~AMDM37x_UART_MCR_TCR_TLR_FLAG;
    122128
    123         /* Restore tcl_lcr */
     129        /* Restore lcr */
    124130        uart->regs->lcr = lcr;
    125131
    126132        /* Disable interrupts */
    127133        uart->regs->ier = 0;
    128 #endif
     134
    129135        /* Setup outdev */
    130136        outdev_initialize("amdm37x_uart_dev", &uart->outdev, &amdm37x_uart_ops);
     
    138144        uart->irq.handler = amdm37x_uart_handler;
    139145        uart->irq.instance = uart;
    140         irq_register(&uart->irq);
    141146
    142147        return true;
     
    148153        /* Set indev */
    149154        uart->indev = indev;
     155        /* Register interrupt. */
     156        irq_register(&uart->irq);
    150157        /* Enable interrupt on receive */
    151158        uart->regs->ier |= AMDM37x_UART_IER_RHR_IRQ_FLAG;
    152 
    153         // TODO set rx fifo
    154         // TODO set rx fifo threshold to 1
    155159}
    156160
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