Changes in boot/arch/arm32/src/mm.c [93d8022:193d280c] in mainline
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boot/arch/arm32/src/mm.c
r93d8022 r193d280c 143 143 pte->should_be_zero_1 = 0; 144 144 pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW; 145 #if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)145 #ifdef PROCESSOR_ARCH_armv7_a 146 146 /* 147 147 * Keeps this setting in sync with memory type attributes in: … … 152 152 pte->tex = section_cacheable(frame) ? 5 : 0; 153 153 pte->cacheable = section_cacheable(frame) ? 0 : 0; 154 pte->bufferable = section_cacheable(frame) ? 1 : 1;154 pte->bufferable = section_cacheable(frame) ? 1 : 0; 155 155 #else 156 pte->bufferable = section_cacheable(frame);156 pte->bufferable = 1; 157 157 pte->cacheable = section_cacheable(frame); 158 158 pte->tex = 0; … … 189 189 */ 190 190 uint32_t val = (uint32_t)boot_pt & TTBR_ADDR_MASK; 191 #if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)192 // FIXME: TTBR_RGN_WBWA_CACHE is unpredictable on ARMv6193 191 val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG; 194 #endif195 192 TTBR0_write(val); 196 193 }
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