Changeset 124bc22 in mainline for kernel/arch/mips32/src/mach/msim/msim.c

Timestamp:

2019-04-04T18:08:51Z (5 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

5d97627

Parents:

e064102

Message:

Reorganize interrupt and IRQ handling on mips32

This allows msim to use MIPS CPU interrupt numbers as IRQ numbers and
Malta to use ISA IRQ numbers as IRQ numbers. Common code can still
register MIPS CPU interrupts by their respective numbers.

File:

• kernel/arch/mips32/src/mach/msim/msim.c (modified) (2 diffs)

kernel/arch/mips32/src/mach/msim/msim.c

@@ -41 +41 @@
 #include <genarch/drivers/dsrln/dsrlnout.h>
 #include <genarch/srln/srln.h>
+#include <stdbool.h>
 
 static void msim_init(void);
@@ -60 +61 @@
 };
 
+static void msim_irq_handler(unsigned int i)
+{
+        irq_t *irq = irq_dispatch_and_lock(i);
+        if (irq) {
+                irq->handler(irq);
+                irq_spinlock_unlock(&irq->lock, false);
+        } else {
+#ifdef CONFIG_DEBUG
+                log(LF_ARCH, LVL_DEBUG, "cpu%u: spurious IRQ (irq=%u)",
+                    CPU->id, i);
+#endif
+        }
+}
+
 void msim_init(void)
 {
+        irq_init(HW_INTERRUPTS, HW_INTERRUPTS);
+
+        int_handler[INT_HW0] = msim_irq_handler;
+        int_handler[INT_HW1] = msim_irq_handler;
+        int_handler[INT_HW2] = msim_irq_handler;
+        int_handler[INT_HW3] = msim_irq_handler;
+        int_handler[INT_HW4] = msim_irq_handler;
+
         dorder_init();
         cp0_unmask_int(MSIM_DDISK_IRQ);