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Ignore:
Timestamp:
2019-04-04T18:08:51Z (2 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master
Children:
5d97627
Parents:
e064102
Message:

Reorganize interrupt and IRQ handling on mips32

This allows msim to use MIPS CPU interrupt numbers as IRQ numbers and
Malta to use ISA IRQ numbers as IRQ numbers. Common code can still
register MIPS CPU interrupts by their respective numbers.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/mips32/include/arch/mach/malta/malta.h

    re064102 r124bc22  
    3939#include <arch/machine_func.h>
    4040#include <arch/mm/page.h>
     41#include <typedefs.h>
    4142
    4243#define MALTA_PCI_BASE          PA2KSEG1(0x18000000UL)
     
    4748
    4849#define TTY_BASE                (MALTA_PCI_BASE + 0x3f8)
    49 #define TTY_CPU_INT             2
    5050#define TTY_ISA_IRQ             4
    5151
    52 #define GT64120_PCI0_INTACK     (MALTA_GT64120_BASE + 0xc34)
     52#define GT64120_PCI0_INTACK     ((ioport32_t *) (MALTA_GT64120_BASE + 0xc34))
    5353
    5454extern struct mips32_machine_ops malta_machine_ops;
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