Changeset 0c40fd5 in mainline for kernel/arch/arm32/include/arch/mm/page_armv6.h
- Timestamp:
- 2013-08-07T18:38:44Z (11 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- ae5fb7c8
- Parents:
- 8ff767b
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/arm32/include/arch/mm/page_armv6.h
r8ff767b r0c40fd5 151 151 * 152 152 * ARM Architecture reference chp. B3.10.1 p. B3-1375 153 * /154 //TODO: DCCMVAU does not work. 153 * @note: see TTRB0/1 for pt memory type 154 */ 155 155 #define pt_coherence_m(pt, count) \ 156 156 do { \ 157 157 for (unsigned i = 0; i < count; ++i) \ 158 DCCMVA C_write((uintptr_t)(pt + i)); \158 DCCMVAU_write((uintptr_t)(pt + i)); \ 159 159 read_barrier(); \ 160 160 } while (0) … … 300 300 p->should_be_zero_0 = 0; 301 301 p->should_be_zero_1 = 0; 302 write_barrier();303 302 p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; 304 303 pt_coherence(p);
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