Changeset 0c40fd5 in mainline for kernel/arch/arm32/include/arch/mm/page_armv4.h

Timestamp:

2013-08-07T18:38:44Z (11 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

ae5fb7c8

Parents:

8ff767b

Message:

arm32: Fix pagetables in cacheable memory.

Set memory attributes in TTBR0/1

File:

• kernel/arch/arm32/include/arch/mm/page_armv4.h (modified) (1 diff)

kernel/arch/arm32/include/arch/mm/page_armv4.h

@@ -120 +120 @@
 #define PTE_DESCRIPTOR_SMALL_PAGE       2
 
-#define pt_coherence_m(page, count)
+#define pt_coherence_m(pt, count) \
+do { \
+        for (unsigned i = 0; i < count; ++i) \
+                DCCMVAU_write((uintptr_t)(pt + i)); \
+        read_barrier(); \
+} while (0)
 
 /** Returns level 0 page table entry flags.