Changeset 0c2d9bb in mainline for uspace/drv/bus/pci/pciintel/pci.c

Timestamp:

2013-12-25T22:54:29Z (10 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

b51cf2c

Parents:

f7a33de (diff), ac36aed (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

merge mainline changes

File:

• uspace/drv/bus/pci/pciintel/pci.c (modified) (16 diffs)

uspace/drv/bus/pci/pciintel/pci.c

@@ -57 +57 @@
 #include <ops/hw_res.h>
 #include <device/hw_res.h>
+#include <ops/pio_window.h>
+#include <device/pio_window.h>
 #include <ddi.h>
 #include <pci_dev_iface.h>
@@ -141 +143 @@
 }
 
+static pio_window_t *pciintel_get_pio_window(ddf_fun_t *fnode)
+{
+        pci_fun_t *fun = pci_fun(fnode);
+        
+        if (fun == NULL)
+                return NULL;
+        return &fun->pio_window;
+}
+
+
 static int pci_config_space_write_32(ddf_fun_t *fun, uint32_t address,
     uint32_t data)
@@ -198 +210 @@
         .get_resource_list = &pciintel_get_resources,
         .enable_interrupt = &pciintel_enable_interrupt,
+};
+
+static pio_window_ops_t pciintel_pio_window_ops = {
+        .get_pio_window = &pciintel_get_pio_window
 };
 
@@ -211 +227 @@
 static ddf_dev_ops_t pci_fun_ops = {
         .interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops,
+        .interfaces[PIO_WINDOW_DEV_IFACE] = &pciintel_pio_window_ops,
         .interfaces[PCI_DEV_IFACE] = &pci_dev_ops
 };
@@ -233 +250 @@
 static void pci_conf_read(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
 {
+        const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
         pci_bus_t *bus = pci_bus_from_fun(fun);
+        uint32_t val;
         
         fibril_mutex_lock(&bus->conf_mutex);
-        
-        const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
-        void *addr = bus->conf_data_port + (reg & 3);
-        
-        pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));
-        
+
+        pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
+
+        /*
+         * Always read full 32-bits from the PCI conf_data_port register and
+         * get the desired portion of it afterwards. Some architectures do not
+         * support shorter PIO reads offset from this register.
+         */
+        val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
+
         switch (len) {
         case 1:
-                /* No endianness change for 1 byte */
-                buf[0] = pio_read_8(addr);
+                *buf = (uint8_t) (val >> ((reg & 3) * 8));
                 break;
         case 2:
-                ((uint16_t *) buf)[0] = uint16_t_le2host(pio_read_16(addr));
+                *((uint16_t *) buf) = (uint16_t) (val >> ((reg & 3)) * 8);
                 break;
         case 4:
-                ((uint32_t *) buf)[0] = uint32_t_le2host(pio_read_32(addr));
+                *((uint32_t *) buf) = (uint32_t) val;
                 break;
         }
@@ -260 +282 @@
 static void pci_conf_write(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
 {
+        const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
         pci_bus_t *bus = pci_bus_from_fun(fun);
+        uint32_t val;
         
         fibril_mutex_lock(&bus->conf_mutex);
-        
-        const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
-        void *addr = bus->conf_data_port + (reg & 3);
-        
-        pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));
+
+        /*
+         * Prepare to write full 32-bits to the PCI conf_data_port register.
+         * Some architectures do not support shorter PIO writes offset from this
+         * register.
+         */
+
+        if (len < 4) {
+                /*
+                 * We have fewer than full 32-bits, so we need to read the
+                 * missing bits first.
+                 */
+                pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
+                val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
+        }
         
         switch (len) {
         case 1:
-                /* No endianness change for 1 byte */
-                pio_write_8(addr, buf[0]);
+                val &= ~(0xffU << ((reg & 3) * 8));
+                val |= *buf << ((reg & 3) * 8);
                 break;
         case 2:
-                pio_write_16(addr, host2uint16_t_le(((uint16_t *) buf)[0]));
+                val &= ~(0xffffU << ((reg & 3) * 8));
+                val |= *((uint16_t *) buf) << ((reg & 3) * 8);
                 break;
         case 4:
-                pio_write_32(addr, host2uint32_t_le(((uint32_t *) buf)[0]));
+                val = *((uint32_t *) buf);
                 break;
         }
+
+        pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
+        pio_write_32(bus->conf_data_reg, host2uint32_t_le(val));
         
         fibril_mutex_unlock(&bus->conf_mutex);
@@ -411 +449 @@
                 hw_resources[count].res.io_range.address = range_addr;
                 hw_resources[count].res.io_range.size = range_size;
+                hw_resources[count].res.io_range.relative = true;
                 hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
         } else {
@@ -416 +455 @@
                 hw_resources[count].res.mem_range.address = range_addr;
                 hw_resources[count].res.mem_range.size = range_size;
+                hw_resources[count].res.mem_range.relative = false;
                 hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
         }
@@ -433 +473 @@
 {
         /* Value of the BAR */
-        uint32_t val, mask;
+        uint32_t val;
+        uint32_t bar;
+        uint32_t mask;
+
         /* IO space address */
         bool io;
@@ -471 +514 @@
         /* Get the address mask. */
         pci_conf_write_32(fun, addr, 0xffffffff);
-        mask &= pci_conf_read_32(fun, addr);
-        
+        bar = pci_conf_read_32(fun, addr);
+
+        /*
+         * Unimplemented BARs read back as all 0's.
+         */
+        if (!bar)
+                return addr + (addrw64 ? 8 : 4);
+
+        mask &= bar;    
+
         /* Restore the original value. */
         pci_conf_write_32(fun, addr, val);
@@ -520 +571 @@
 {
         uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE);
-        if (irq != 0xff)
+        uint8_t pin = pci_conf_read_8(fun, PCI_BRIDGE_INT_PIN);
+
+        if (pin != 0 && irq != 0xff)
                 pci_add_interrupt(fun, irq);
 }
@@ -583 +636 @@
                         pci_read_bars(fun);
                         pci_read_interrupt(fun);
+
+                        /* Propagate the PIO window to the function. */
+                        fun->pio_window = bus->pio_win;
                         
                         ddf_fun_set_ops(fun->fnode, &pci_fun_ops);
@@ -613 +669 @@
 static int pci_dev_add(ddf_dev_t *dnode)
 {
+        hw_resource_list_t hw_resources;
         pci_bus_t *bus = NULL;
         ddf_fun_t *ctl = NULL;
@@ -638 +695 @@
                 goto fail;
         }
-        
-        hw_resource_list_t hw_resources;
+
+        rc = pio_window_get(sess, &bus->pio_win);
+        if (rc != EOK) {
+                ddf_msg(LVL_ERROR, "pci_dev_add failed to get PIO window "
+                    "for the device.");
+                goto fail;
+        }
         
         rc = hw_res_get_resource_list(sess, &hw_resources);
@@ -662 +724 @@
             hw_resources.resources[1].res.io_range.address);
         
-        bus->conf_io_addr =
-            (uint32_t) hw_resources.resources[0].res.io_range.address;
-        bus->conf_io_data =
-            (uint32_t) hw_resources.resources[1].res.io_range.address;
-        
-        if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 4,
-            &bus->conf_addr_port)) {
+        if (pio_enable_resource(&bus->pio_win, &hw_resources.resources[0],
+            (void **) &bus->conf_addr_reg)) {
                 ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
                 rc = EADDRNOTAVAIL;
                 goto fail;
         }
-        if (pio_enable((void *)(uintptr_t)bus->conf_io_data, 4,
-            &bus->conf_data_port)) {
+        if (pio_enable_resource(&bus->pio_win, &hw_resources.resources[1],
+            (void **) &bus->conf_data_reg)) {
                 ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
                 rc = EADDRNOTAVAIL;
@@ -729 +786 @@
 {
         ddf_log_init(NAME);
-        pci_fun_ops.interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops;
-        pci_fun_ops.interfaces[PCI_DEV_IFACE] = &pci_dev_ops;
 }