Changeset 0c12dfe in mainline

Timestamp:

2012-11-20T12:57:46Z (11 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

9c0eba6

Parents:

68338c6

Message:

typos and comments

Location:

uspace/drv/infrastructure/rootamdm37x

Files:

• cm/mpu.h (modified) (1 diff)
• rootamdm37x.c (modified) (3 diffs)

uspace/drv/infrastructure/rootamdm37x/cm/mpu.h

@@ -87 +87 @@
 
         const ioport32_t clkstst;
-#define MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTICE_FLAG   (1 << 0)
+#define MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTIVE_FLAG   (1 << 0)
 
 } mpu_cm_regs_t;

uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c

@@ -155 +155 @@
 
         /* Current MPU frequency. */
-        if (pio_read_32(&mpu->clkstst) & MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTICE_FLAG) {
+        if (pio_read_32(&mpu->clkstst) & MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTIVE_FLAG) {
                 if (pio_read_32(&mpu->idlest_pll) & MPU_CM_IDLEST_PLL_ST_MPU_CLK_LOCKED_FLAG) {
                         /* DPLL active and locked */
@@ -224 +224 @@
          * we can probably turn this off entirely (DSS is still non-functional).
          */
-        /* Set DPLL4 to automatic to save power*/
+        /* Set DPLL4 to automatic to save power */
         pio_change_32(&device->cm.clocks->autoidle_pll,
             CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC,
@@ -234 +234 @@
          */
         // TODO setup DPLL5
-        /* Set DPLL5 to automatic */
+        /* Set DPLL5 to automatic to save power */
         pio_change_32(&device->cm.clocks->autoidle2_pll,
             CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_AUTOMATIC,