Changeset 0b9ac3c in mainline for kernel/arch/amd64/include/atomic.h

Timestamp:

2010-02-23T19:03:28Z (14 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

c62d2e1

Parents:

1ccafee (diff), 5e50394 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge mainline changes.

File:

• kernel/arch/amd64/include/atomic.h (modified) (7 diffs)

kernel/arch/amd64/include/atomic.h

@@ -40 +40 @@
 #include <preemption.h>
 
-static inline void atomic_inc(atomic_t *val) {
+static inline void atomic_inc(atomic_t *val)
+{
 #ifdef CONFIG_SMP
         asm volatile (
@@ -54 +55 @@
 }
 
-static inline void atomic_dec(atomic_t *val) {
+static inline void atomic_dec(atomic_t *val)
+{
 #ifdef CONFIG_SMP
         asm volatile (
@@ -68 +70 @@
 }
 
-static inline long atomic_postinc(atomic_t *val) 
+static inline atomic_count_t atomic_postinc(atomic_t *val)
 {
-        long r = 1;
+        atomic_count_t r = 1;
         
         asm volatile (
                 "lock xaddq %[r], %[count]\n"
-                : [count] "+m" (val->count), [r] "+r" (r)
+                : [count] "+m" (val->count),
+                  [r] "+r" (r)
         );
         
@@ -80 +83 @@
 }
 
-static inline long atomic_postdec(atomic_t *val) 
+static inline atomic_count_t atomic_postdec(atomic_t *val)
 {
-        long r = -1;
+        atomic_count_t r = -1;
         
         asm volatile (
                 "lock xaddq %[r], %[count]\n"
-                : [count] "+m" (val->count), [r] "+r" (r)
+                : [count] "+m" (val->count),
+                  [r] "+r" (r)
         );
         
@@ -95 +99 @@
 #define atomic_predec(val)  (atomic_postdec(val) - 1)
 
-static inline uint64_t test_and_set(atomic_t *val) {
-        uint64_t v;
+static inline atomic_count_t test_and_set(atomic_t *val)
+{
+        atomic_count_t v = 1;
         
         asm volatile (
-                "movq $1, %[v]\n"
                 "xchgq %[v], %[count]\n"
-                : [v] "=r" (v), [count] "+m" (val->count)
+                : [v] "+r" (v),
+                  [count] "+m" (val->count)
         );
         
@@ -107 +112 @@
 }
 
-
 /** amd64 specific fast spinlock */
 static inline void atomic_lock_arch(atomic_t *val)
 {
-        uint64_t tmp;
+        atomic_count_t tmp;
         
         preemption_disable();
@@ -125 +129 @@
                 "testq %[tmp], %[tmp]\n"
                 "jnz 0b\n"
-                : [count] "+m" (val->count), [tmp] "=&r" (tmp)
+                : [count] "+m" (val->count),
+                  [tmp] "=&r" (tmp)
         );
+        
         /*
          * Prevent critical section code from bleeding out this way up.