Changeset 07d62a9 in mainline


Ignore:
Timestamp:
2013-01-11T01:28:21Z (11 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
bedd81b
Parents:
eb1d9c1
Message:

arm32: remove debug output.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm32/src/fpu_context.c

    reb1d9c1 r07d62a9  
    170170                } else {
    171171                        uint32_t nsacr = NSACR_read();
    172                         nsacr |= NSACR_CP_FLAG(10) | NSACR_CP_FLAG(11);
     172                        nsacr |= (NSACR_CP_FLAG(10) | NSACR_CP_FLAG(11));
    173173                        NSACR_write(nsacr);
    174                         printf("NSACR: %x => %x\n", nsacr, NSACR_read());
    175174                        smc_coherence(0);
    176175                }
     
    179178        /* Allow coprocessor access */
    180179        uint32_t cpacr = CPACR_read();
    181         printf("CPACR before: %x\n", cpacr);
    182180        /* FPU needs access to coprocessor 10 and 11.
    183181         * Moreover, they need to have same access enabled */
    184182        cpacr &= ~(CPACR_CP_MASK(10) | CPACR_CP_MASK(11));
    185         cpacr |= CPACR_CP_FULL_ACCESS(10) | CPACR_CP_FULL_ACCESS(11);
     183        cpacr |= (CPACR_CP_FULL_ACCESS(10) | CPACR_CP_FULL_ACCESS(11));
    186184        CPACR_write(cpacr);
    187         printf("CPACR after: %x\n", cpacr);
    188185
    189186        smc_coherence(0);
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