Changeset 0773396 in mainline for kernel/genarch/include/genarch/drivers/amdm37x/irc.h
- Timestamp:
- 2013-12-25T13:05:25Z (10 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- bc54126c
- Parents:
- f4a47e52 (diff), 6946f23 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)
links above to see all the changes relative to each parent. - File:
-
- 1 edited
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kernel/genarch/include/genarch/drivers/amdm37x/irc.h
rf4a47e52 r0773396 38 38 39 39 /* AMDM37x TRM p. 1079 */ 40 #define AMDM37x_IRC_BASE_ADDRESS 0x4820000041 #define AMDM37x_IRC_SIZE 409640 #define AMDM37x_IRC_BASE_ADDRESS 0x48200000 41 #define AMDM37x_IRC_SIZE 4096 42 42 43 #define AMDM37x_IRC_IRQ_COUNT 96 43 #define AMDM37x_IRC_IRQ_COUNT 96 44 #define AMDM37x_IRC_IRQ_GROUPS_COUNT 3 44 45 45 #include <typedefs.h> 46 #define OMAP_IRC_IRQ_COUNT AMDM37x_IRC_IRQ_COUNT 47 #define OMAP_IRC_IRQ_GROUPS_COUNT AMDM37x_IRC_IRQ_GROUPS_COUNT 46 48 47 typedef struct { 48 const ioport32_t revision; /**< Revision */ 49 #define AMDM37x_IRC_REV_MASK (0xff) 50 51 uint8_t padd0_[12]; 52 53 ioport32_t sysconfig; /**< SYS config */ 54 #define AMDM37x_IRC_SYSCONFIG_AUTOIDLE_FLAG (1 << 0) 55 #define AMDM37x_IRC_SYSCONFIG_SOFTRESET_FLAG (1 << 1) 56 57 const ioport32_t sysstatus; /**< SYS status */ 58 #define AMDM37x_IRC_SYSSTATUS_RESET_DONE_FLAG (1 << 0) 59 60 uint8_t padd1_[40]; 61 62 const ioport32_t sir_irq; /**< Currently active irq number */ 63 #define AMDM37x_IRC_SIR_IRQ_ACTIVEIRQ_MASK (0x7f) 64 #define AMDM37x_IRC_SIR_IRQ_SPURIOUSIRQFLAG_MASK (0xfffffff8) 65 66 const ioport32_t sir_fiq; 67 #define AMDM37x_IRC_SIR_FIQ_ACTIVEIRQ_MASK (0x7f) 68 #define AMDM37x_IRC_SIR_FIQ_SPURIOUSIRQFLAG_MASK (0xfffffff8) 69 70 ioport32_t control; /**< New interrupt agreement. */ 71 #define AMDM37x_IRC_CONTROL_NEWIRQAGR_FLAG (1 << 0) 72 #define AMDM37x_IRC_CONTROL_NEWFIQAGR_FLAG (1 << 1) 73 74 ioport32_t protection; /**< Protect other registers. */ 75 #define AMDM37x_IRC_PROTECTION_PROETCTION_FLAG (1 << 0) 76 77 ioport32_t idle; /**< Idle and autogating */ 78 #define AMDM37x_IRC_IDLE_FUNCIDLE_FLAG (1 << 0) 79 #define AMDM37x_IRC_IDLE_TURBO_FLAG (1 << 1) 80 81 uint8_t padd2_[12]; 82 83 ioport32_t irq_priority; /**< Active IRQ priority */ 84 #define AMDM37x_IRC_IRQ_PRIORITY_IRQPRIORITY_MASK (0x7f) 85 #define AMDM37x_IRC_IRQ_PRIORITY_SPURIOUSIRQFLAG_MASK (0xfffffff8) 86 87 ioport32_t fiq_priority; /**< Active FIQ priority */ 88 #define AMDM37x_IRC_FIQ_PRIORITY_FIQPRIORITY_MASK (0x7f) 89 #define AMDM37x_IRC_FIQ_PRIORITY_SPURIOUSFIQFLAG_MASK (0xfffffff8) 90 91 ioport32_t threshold; /**< Priority threshold */ 92 #define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_MASK (0xff) 93 #define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_ENABLED (0x00) 94 #define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_DISABLED (0xff) 95 96 uint8_t padd3__[20]; 97 98 struct { 99 const ioport32_t itr; /**< Interrupt input status before masking */ 100 ioport32_t mir; /**< Interrupt mask */ 101 ioport32_t mir_clear; /**< Clear mir mask bits */ 102 ioport32_t mir_set; /**< Set mir mask bits */ 103 ioport32_t isr_set; /**< Set software interrupt bits */ 104 ioport32_t isr_clear; /**< Clear software interrupt bits */ 105 const ioport32_t pending_irq; /**< IRQ status after masking */ 106 const ioport32_t pending_fiq; /**< FIQ status after masking */ 107 } interrupts[3]; 108 109 uint8_t padd4_[32]; 110 111 ioport32_t ilr[96]; /**< FIQ/IRQ steering */ 112 #define AMDM37x_IRC_ILR_FIQNIRQ (1 << 0) 113 #define AMDM37x_IRC_ILR_PRIORITY_MASK (0x3f) 114 #define AMDM37x_IRC_ILR_PRIORITY_SHIFT (2) 115 116 } amdm37x_irc_regs_t; 117 118 static inline void amdm37x_irc_dump(amdm37x_irc_regs_t *regs) 119 { 120 #define DUMP_REG(name) \ 121 printf("%s %p(%x).\n", #name, ®s->name, regs->name); 122 123 DUMP_REG(revision); 124 DUMP_REG(sysconfig); 125 DUMP_REG(sysstatus); 126 DUMP_REG(sir_irq); 127 DUMP_REG(sir_fiq); 128 DUMP_REG(control); 129 DUMP_REG(protection); 130 DUMP_REG(idle); 131 DUMP_REG(irq_priority); 132 DUMP_REG(fiq_priority); 133 DUMP_REG(threshold); 134 135 for (int i = 0; i < 3; ++i) { 136 DUMP_REG(interrupts[i].itr); 137 DUMP_REG(interrupts[i].mir); 138 DUMP_REG(interrupts[i].isr_set); 139 DUMP_REG(interrupts[i].pending_irq); 140 DUMP_REG(interrupts[i].pending_fiq); 141 } 142 for (int i = 0; i < AMDM37x_IRC_IRQ_COUNT; ++i) { 143 DUMP_REG(ilr[i]); 144 } 145 146 #undef DUMP_REG 147 } 148 149 static inline void amdm37x_irc_init(amdm37x_irc_regs_t *regs) 150 { 151 /* AMDM37x TRM sec 12.5.1 p. 2425 */ 152 /* Program system config register */ 153 //TODO enable this when you know the meaning 154 //regs->sysconfig |= AMDM37x_IRC_SYSCONFIG_AUTOIDLE_FLAG; 155 156 /* Program idle register */ 157 //TODO enable this when you know the meaning 158 //regs->sysconfig |= AMDM37x_IRC_IDLE_TURBO_FLAG; 159 160 /* Program ilr[m] assign priority, decide fiq */ 161 for (unsigned i = 0; i < AMDM37x_IRC_IRQ_COUNT; ++i) { 162 regs->ilr[i] = 0; /* highest prio(default) route to irq */ 163 } 164 165 /* Disable all interrupts */ 166 regs->interrupts[0].mir_set = 0xffffffff; 167 regs->interrupts[1].mir_set = 0xffffffff; 168 regs->interrupts[2].mir_set = 0xffffffff; 169 } 170 171 static inline unsigned amdm37x_irc_inum_get(amdm37x_irc_regs_t *regs) 172 { 173 return regs->sir_irq & AMDM37x_IRC_SIR_IRQ_ACTIVEIRQ_MASK; 174 } 175 176 static inline void amdm37x_irc_irq_ack(amdm37x_irc_regs_t *regs) 177 { 178 regs->control = AMDM37x_IRC_CONTROL_NEWIRQAGR_FLAG; 179 } 180 181 static inline void amdm37x_irc_fiq_ack(amdm37x_irc_regs_t *regs) 182 { 183 regs->control = AMDM37x_IRC_CONTROL_NEWFIQAGR_FLAG; 184 } 185 186 static inline void amdm37x_irc_enable(amdm37x_irc_regs_t *regs, unsigned inum) 187 { 188 ASSERT(inum < AMDM37x_IRC_IRQ_COUNT); 189 const unsigned set = inum / 32; 190 const unsigned pos = inum % 32; 191 regs->interrupts[set].mir_clear = (1 << pos); 192 } 193 194 static inline void amdm37x_irc_disable(amdm37x_irc_regs_t *regs, unsigned inum) 195 { 196 ASSERT(inum < AMDM37x_IRC_IRQ_COUNT); 197 const unsigned set = inum / 32; 198 const unsigned pos = inum % 32; 199 regs->interrupts[set].mir_set = (1 << pos); 200 } 49 #include <genarch/drivers/omap/irc.h> 201 50 202 51 #endif
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