Changes in kernel/arch/arm64/src/start.S [84176f3:06f10ac] in mainline
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kernel/arch/arm64/src/start.S (modified) (5 diffs)
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kernel/arch/arm64/src/start.S
r84176f3 r06f10ac 35 35 .section K_TEXT_START, "ax" 36 36 37 .macro dcache_flush addr size temp0 temp1 38 mov \temp0, \addr 39 mov \temp1, xzr 40 41 0: 42 /* Data or Unified Cache Line Clean */ 43 dc cvau, \temp0 44 add \temp0, \temp0, #4 45 add \temp1, \temp1, #4 46 cmp \temp1, \size 47 blo 0b 48 49 dsb ish 50 isb 51 .endm 52 53 /** Kernel entry 54 * 55 * MMU must be disabled at this point. 56 * 57 * @param x0 Kernel entry point (kernel_image_start). 58 * @param x1 Pointer to the bootinfo structure. 59 * 60 */ 37 61 SYMBOL(kernel_image_start) 38 /*39 * Parameters:40 * x0 is kernel entry point (kernel_image_start).41 * x1 is pointer to the bootinfo structure.42 *43 * MMU must be disabled at this point.44 */45 46 62 /* Get address of the main memory and remember it. */ 47 63 adrp x20, kernel_image_start - BOOT_OFFSET 48 64 adrp x2, physmem_base 49 /* add x2, x2, #:lo12:physmem_base */50 65 str x20, [x2] 51 66 52 /* 53 * Set up address translation that identity maps the gigabyte area that 67 /* Flush the data cache of physmem_base. */ 68 mov x28, #8 69 dcache_flush x2 x28 x29 x30 70 71 /* 72 * Set up address translation that identity maps the 1 GiB area that 54 73 * is holding the current execution page. 55 74 */ … … 76 95 mov x3, #( \ 77 96 1 << PTE_ACCESS_SHIFT | \ 78 MAIR_EL1_ DEVICE_MEMORY_INDEX << PTE_ATTR_INDEX_SHIFT | \97 MAIR_EL1_NORMAL_MEMORY_INDEX << PTE_ATTR_INDEX_SHIFT | \ 79 98 PTE_L012_TYPE_BLOCK << PTE_TYPE_SHIFT | \ 80 99 1 << PTE_PRESENT_SHIFT) … … 84 103 85 104 /* 86 * Set up address translation that maps the first gigabyteof the kernel87 * identity virtual address space to the first gigabyteof the physical105 * Set up address translation that maps the first 4 GiB of the kernel 106 * identity virtual address space to the first 4 GiB of the physical 88 107 * memory. 89 108 */ 90 109 91 110 mov x21, #KM_ARM64_IDENTITY_START 111 ldr x22, =(1024 * 1024 * 1024) 92 112 93 113 /* Prepare the level 0 page table. */ … … 112 132 mov x3, #( \ 113 133 1 << PTE_ACCESS_SHIFT | \ 134 MAIR_EL1_NORMAL_MEMORY_INDEX << PTE_ATTR_INDEX_SHIFT | \ 135 PTE_L012_TYPE_BLOCK << PTE_TYPE_SHIFT | \ 136 1 << PTE_PRESENT_SHIFT) 137 lsr x4, x20, #FRAME_WIDTH 138 orr x3, x3, x4, lsl #PTE_OUTPUT_ADDRESS_SHIFT 139 str x3, [x2] 140 141 /* 2nd GiB */ 142 add x23, x20, x22 143 add x24, x21, x22 144 145 adrp x2, upper_page_table_level1 146 lsr x3, x24, #PTL1_VA_SHIFT 147 and x3, x3, #PTL1_VA_MASK 148 add x2, x2, x3, lsl #PTL_ENTRY_SIZE_SHIFT 149 mov x3, #( \ 150 1 << PTE_ACCESS_SHIFT | \ 151 MAIR_EL1_NORMAL_MEMORY_INDEX << PTE_ATTR_INDEX_SHIFT | \ 152 PTE_L012_TYPE_BLOCK << PTE_TYPE_SHIFT | \ 153 1 << PTE_PRESENT_SHIFT) 154 lsr x4, x23, #FRAME_WIDTH 155 orr x3, x3, x4, lsl #PTE_OUTPUT_ADDRESS_SHIFT 156 str x3, [x2] 157 158 /* 3rd GiB */ 159 add x23, x23, x22 160 add x24, x24, x22 161 162 adrp x2, upper_page_table_level1 163 lsr x3, x24, #PTL1_VA_SHIFT 164 and x3, x3, #PTL1_VA_MASK 165 add x2, x2, x3, lsl #PTL_ENTRY_SIZE_SHIFT 166 mov x3, #( \ 167 1 << PTE_ACCESS_SHIFT | \ 168 MAIR_EL1_NORMAL_MEMORY_INDEX << PTE_ATTR_INDEX_SHIFT | \ 169 PTE_L012_TYPE_BLOCK << PTE_TYPE_SHIFT | \ 170 1 << PTE_PRESENT_SHIFT) 171 lsr x4, x23, #FRAME_WIDTH 172 orr x3, x3, x4, lsl #PTE_OUTPUT_ADDRESS_SHIFT 173 str x3, [x2] 174 175 /* 4th GiB */ 176 add x23, x23, x22 177 add x24, x24, x22 178 179 adrp x2, upper_page_table_level1 180 lsr x3, x24, #PTL1_VA_SHIFT 181 and x3, x3, #PTL1_VA_MASK 182 add x2, x2, x3, lsl #PTL_ENTRY_SIZE_SHIFT 183 mov x3, #( \ 184 1 << PTE_ACCESS_SHIFT | \ 114 185 MAIR_EL1_DEVICE_MEMORY_INDEX << PTE_ATTR_INDEX_SHIFT | \ 115 186 PTE_L012_TYPE_BLOCK << PTE_TYPE_SHIFT | \ 116 187 1 << PTE_PRESENT_SHIFT) 117 lsr x4, x20, #FRAME_WIDTH 118 orr x3, x3, x4, lsl #PTE_OUTPUT_ADDRESS_SHIFT 119 str x3, [x2] 188 lsr x4, x23, #FRAME_WIDTH 189 orr x3, x3, x4, lsl #PTE_OUTPUT_ADDRESS_SHIFT 190 str x3, [x2] 191 192 /* Flush the data cache of page tables. */ 193 adrp x27, lower_page_table_level0 194 mov x28, #4096 195 dcache_flush x27 x28 x29 x30 196 197 adrp x27, lower_page_table_level1 198 mov x28, #4096 199 dcache_flush x27 x28 x29 x30 200 201 adrp x27, upper_page_table_level0 202 mov x28, #4096 203 dcache_flush x27 x28 x29 x30 204 205 adrp x27, upper_page_table_level1 206 mov x28, #4096 207 dcache_flush x27 x28 x29 x30 120 208 121 209 /* Make sure there are not any stale TLB entries. */ … … 271 359 lower_page_table_level0: 272 360 .space 4096 361 273 362 lower_page_table_level1: 274 363 .space 4096 364 275 365 upper_page_table_level0: 276 366 .space 4096 367 277 368 upper_page_table_level1: 278 369 .space 4096
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