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Changeset 06f10ac in mainline for kernel/arch/arm64/src/start.S


Ignore:
Timestamp:
2021-08-22T19:08:44Z (2 months ago)
Author:
Martin Decky <martin@…>
Branches:
master
Children:
c21cc26
Parents:
95b7d4df
Message:

Implement support for HiKey? 960

Initial support for the 96Boards HiKey? 960 board.

  • The kernel identity mapping has been extended to 4 GiB. The initial bootstrap mapping maps 3 GiB as nornal memory and the next 1 GiB as device memory to support early UART debugging output.
  • The istate_t has been padded in order to preserve the stack pointer alignment invariant.

The current implementation is limited to UP and UART input/output.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm64/src/start.S

    r95b7d4df r06f10ac  
    3535.section K_TEXT_START, "ax"
    3636
     37.macro dcache_flush addr size temp0 temp1
     38        mov \temp0, \addr
     39        mov \temp1, xzr
     40
     41        0:
     42                /* Data or Unified Cache Line Clean */
     43                dc cvau, \temp0
     44                add \temp0, \temp0, #4
     45                add \temp1, \temp1, #4
     46                cmp \temp1, \size
     47                blo 0b
     48
     49        dsb ish
     50        isb
     51.endm
     52
     53/** Kernel entry
     54 *
     55 * MMU must be disabled at this point.
     56 *
     57 * @param x0 Kernel entry point (kernel_image_start).
     58 * @param x1 Pointer to the bootinfo structure.
     59 *
     60 */
    3761SYMBOL(kernel_image_start)
    38         /*
    39          * Parameters:
    40          * x0 is kernel entry point (kernel_image_start).
    41          * x1 is pointer to the bootinfo structure.
    42          *
    43          * MMU must be disabled at this point.
    44          */
    45 
    4662        /* Get address of the main memory and remember it. */
    4763        adrp x20, kernel_image_start - BOOT_OFFSET
    4864        adrp x2, physmem_base
    49         /* add x2, x2, #:lo12:physmem_base */
    5065        str x20, [x2]
    5166
    52         /*
    53          * Set up address translation that identity maps the gigabyte area that
     67        /* Flush the data cache of physmem_base. */
     68        mov x28, #8
     69        dcache_flush x2 x28 x29 x30
     70
     71        /*
     72         * Set up address translation that identity maps the 1 GiB area that
    5473         * is holding the current execution page.
    5574         */
     
    7695        mov x3, #( \
    7796            1 << PTE_ACCESS_SHIFT | \
    78             MAIR_EL1_DEVICE_MEMORY_INDEX << PTE_ATTR_INDEX_SHIFT | \
     97            MAIR_EL1_NORMAL_MEMORY_INDEX << PTE_ATTR_INDEX_SHIFT | \
    7998            PTE_L012_TYPE_BLOCK << PTE_TYPE_SHIFT | \
    8099            1 << PTE_PRESENT_SHIFT)
     
    84103
    85104        /*
    86          * Set up address translation that maps the first gigabyte of the kernel
    87          * identity virtual address space to the first gigabyte of the physical
     105         * Set up address translation that maps the first 4 GiB of the kernel
     106         * identity virtual address space to the first 4 GiB of the physical
    88107         * memory.
    89108         */
    90109
    91110        mov x21, #KM_ARM64_IDENTITY_START
     111        ldr x22, =(1024 * 1024 * 1024)
    92112
    93113        /* Prepare the level 0 page table. */
     
    112132        mov x3, #( \
    113133            1 << PTE_ACCESS_SHIFT | \
     134            MAIR_EL1_NORMAL_MEMORY_INDEX << PTE_ATTR_INDEX_SHIFT | \
     135            PTE_L012_TYPE_BLOCK << PTE_TYPE_SHIFT | \
     136            1 << PTE_PRESENT_SHIFT)
     137        lsr x4, x20, #FRAME_WIDTH
     138        orr x3, x3, x4, lsl #PTE_OUTPUT_ADDRESS_SHIFT
     139        str x3, [x2]
     140
     141        /* 2nd GiB */
     142        add x23, x20, x22
     143        add x24, x21, x22
     144
     145        adrp x2, upper_page_table_level1
     146        lsr x3, x24, #PTL1_VA_SHIFT
     147        and x3, x3, #PTL1_VA_MASK
     148        add x2, x2, x3, lsl #PTL_ENTRY_SIZE_SHIFT
     149        mov x3, #( \
     150            1 << PTE_ACCESS_SHIFT | \
     151            MAIR_EL1_NORMAL_MEMORY_INDEX << PTE_ATTR_INDEX_SHIFT | \
     152            PTE_L012_TYPE_BLOCK << PTE_TYPE_SHIFT | \
     153            1 << PTE_PRESENT_SHIFT)
     154        lsr x4, x23, #FRAME_WIDTH
     155        orr x3, x3, x4, lsl #PTE_OUTPUT_ADDRESS_SHIFT
     156        str x3, [x2]
     157
     158        /* 3rd GiB */
     159        add x23, x23, x22
     160        add x24, x24, x22
     161
     162        adrp x2, upper_page_table_level1
     163        lsr x3, x24, #PTL1_VA_SHIFT
     164        and x3, x3, #PTL1_VA_MASK
     165        add x2, x2, x3, lsl #PTL_ENTRY_SIZE_SHIFT
     166        mov x3, #( \
     167            1 << PTE_ACCESS_SHIFT | \
     168            MAIR_EL1_NORMAL_MEMORY_INDEX << PTE_ATTR_INDEX_SHIFT | \
     169            PTE_L012_TYPE_BLOCK << PTE_TYPE_SHIFT | \
     170            1 << PTE_PRESENT_SHIFT)
     171        lsr x4, x23, #FRAME_WIDTH
     172        orr x3, x3, x4, lsl #PTE_OUTPUT_ADDRESS_SHIFT
     173        str x3, [x2]
     174
     175        /* 4th GiB */
     176        add x23, x23, x22
     177        add x24, x24, x22
     178
     179        adrp x2, upper_page_table_level1
     180        lsr x3, x24, #PTL1_VA_SHIFT
     181        and x3, x3, #PTL1_VA_MASK
     182        add x2, x2, x3, lsl #PTL_ENTRY_SIZE_SHIFT
     183        mov x3, #( \
     184            1 << PTE_ACCESS_SHIFT | \
    114185            MAIR_EL1_DEVICE_MEMORY_INDEX << PTE_ATTR_INDEX_SHIFT | \
    115186            PTE_L012_TYPE_BLOCK << PTE_TYPE_SHIFT | \
    116187            1 << PTE_PRESENT_SHIFT)
    117         lsr x4, x20, #FRAME_WIDTH
    118         orr x3, x3, x4, lsl #PTE_OUTPUT_ADDRESS_SHIFT
    119         str x3, [x2]
     188        lsr x4, x23, #FRAME_WIDTH
     189        orr x3, x3, x4, lsl #PTE_OUTPUT_ADDRESS_SHIFT
     190        str x3, [x2]
     191
     192        /* Flush the data cache of page tables. */
     193        adrp x27, lower_page_table_level0
     194        mov x28, #4096
     195        dcache_flush x27 x28 x29 x30
     196
     197        adrp x27, lower_page_table_level1
     198        mov x28, #4096
     199        dcache_flush x27 x28 x29 x30
     200
     201        adrp x27, upper_page_table_level0
     202        mov x28, #4096
     203        dcache_flush x27 x28 x29 x30
     204
     205        adrp x27, upper_page_table_level1
     206        mov x28, #4096
     207        dcache_flush x27 x28 x29 x30
    120208
    121209        /* Make sure there are not any stale TLB entries. */
     
    271359lower_page_table_level0:
    272360        .space 4096
     361
    273362lower_page_table_level1:
    274363        .space 4096
     364
    275365upper_page_table_level0:
    276366        .space 4096
     367
    277368upper_page_table_level1:
    278369        .space 4096
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