Changeset 06f10ac in mainline for kernel/arch/arm64/src/asm.S

Timestamp:

2021-08-22T19:08:44Z (3 years ago)

Author:

Martin Decky <martin@…>

Branches:

master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

c21cc26

Parents:

95b7d4df

Message:

Implement support for HiKey 960

Initial support for the 96Boards HiKey 960 board.

• The kernel identity mapping has been extended to 4 GiB. The initial bootstrap mapping maps 3 GiB as nornal memory and the next 1 GiB as device memory to support early UART debugging output.

• The istate_t has been padded in order to preserve the stack pointer alignment invariant.

The current implementation is limited to UP and UART input/output.

File:

• kernel/arch/arm64/src/asm.S (modified) (1 diff)

kernel/arch/arm64/src/asm.S

@@ -59 +59 @@
         ret
 FUNCTION_END(early_putuchar)
+
+/** Flush instruction caches
+ *
+ * @param x0 Starting address of the flushing.
+ * @param x1 Number of bytes to flush.
+ *
+ */
+FUNCTION_BEGIN(smc_coherence)
+        /* Initialize loop */
+        mov x9, x0
+        mov x10, xzr
+
+        __dc_loop:
+                /* Data or Unified Cache Line Clean */
+                dc cvau, x9
+                add x9, x9, #4
+                add x10, x10, #4
+                cmp x10, x1
+                blo __dc_loop
+
+        dsb ish
+
+        /* Initialize loop */
+        mov x9, x0
+        mov x10, xzr
+
+        __ic_loop:
+                /* Instruction Cache Line Invalidate */
+                ic ivau, x9
+                add x9, x9, #4
+                add x10, x10, #4
+                cmp x10, x1
+                blo __ic_loop
+
+        dsb ish
+        isb
+        ret
+FUNCTION_END(smc_coherence)
 
 /* Static checks for the istate_t save/load. */