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  • kernel/arch/arm64/include/arch/barrier.h

    r84176f3 r06f10ac  
    3737#define KERN_arm64_BARRIER_H_
    3838
    39 #include <stddef.h>
    40 
    41 #define COHERENCE_INVAL_MIN  4
    42 
    43 /** Ensure visibility of instruction updates for a multiprocessor.
    44  *
    45  * @param addr Address of the first instruction.
    46  * @param size Size of the instruction block (in bytes).
    47  */
    48 static inline void ensure_visibility(void *addr, size_t len)
    49 {
    50         size_t i;
    51 
    52         /*
    53          * Clean to Point of Unification to make the new instructions visible to
    54          * the instruction cache.
    55          */
    56         for (i = 0; i < len; i += COHERENCE_INVAL_MIN)
    57                 asm volatile (
    58                     "dc cvau, %[addr]\n"
    59                     : : [addr] "r" ((char *) addr + i)
    60                 );
    61 
    62         /* Ensure completion on all PEs. */
    63         asm volatile ("dsb ish" ::: "memory");
    64 
    65         /* Ensure instruction cache/branch predictor discards stale data. */
    66         for (i = 0; i < len; i += COHERENCE_INVAL_MIN)
    67                 asm volatile (
    68                     "ic ivau, %[addr]\n"
    69                     : : [addr] "r" ((char *) addr + i)
    70                 );
    71 
    72         /* Ensure completion on all PEs. */
    73         asm volatile ("dsb ish" ::: "memory");
    74 
    75         /* Synchronize context on this PE. */
    76         asm volatile ("isb");
    77 }
    78 
    7939#endif
    8040
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