Index: boot/arch/arm32/src/asm.S
===================================================================
--- boot/arch/arm32/src/asm.S	(revision 5265eea4b6e13925ae465dd16a7d61a8c7dd994d)
+++ boot/arch/arm32/src/asm.S	(revision 03289871c675b83ed939beb60680fb3245e1eea6)
@@ -75,18 +75,18 @@
 	bic	r4, r4, #(1 << CP15_C1_DC)
 
-	# Disable I-cache and Branch predictors.
+	# Disable I-cache and Branche predictors.
 	bic	r4, r4, #(1 << CP15_C1_IC)
-#ifdef PROCESSOR_ARCH_armv6
 	bic	r4, r4, #(1 << CP15_C1_BP)
-#endif
 	
 	mcr	p15, 0, r4, c1, c0, 0
 #endif
+
+
 	
-	# Wait for the operations to complete
+	#Wait for the operations to complete
 #ifdef PROCESSOR_ARCH_armv7_a
 	dsb
 #else
-	# cp15 dsb, r4 is ignored (should be zero)
+	#cp15 dsb, r4 is ignored (should be zero)
 	mov r4, #0
 	mcr p15, 0, r4, c7, c10, 4
@@ -98,9 +98,9 @@
 	nop
 
-	# Wait for the operations to complete
+	#Wait for the operations to complete
 #ifdef PROCESSOR_ARCH_armv7_a
 	isb
 	nop
-#elif defined(PROCESSOR_ARCH_armv6)
+#else
 	# cp15 isb
 	mcr p15, 0, r4, c7, c5, 4
Index: boot/arch/arm32/src/main.c
===================================================================
--- boot/arch/arm32/src/main.c	(revision 5265eea4b6e13925ae465dd16a7d61a8c7dd994d)
+++ boot/arch/arm32/src/main.c	(revision 03289871c675b83ed939beb60680fb3245e1eea6)
@@ -47,5 +47,4 @@
 #include <errno.h>
 #include <inflate.h>
-#include <arch/cp15.h>
 
 #define TOP2ADDR(top)  (((void *) PA2KA(BOOT_OFFSET)) + (top))
@@ -56,26 +55,8 @@
 static inline void clean_dcache_poc(void *address, size_t size)
 {
-	const uintptr_t addr = (uintptr_t) address;
-
-#if !defined(PROCESSOR_ARCH_armv7_a)
-	bool sep;
-	if (MIDR_read() != CTR_read()) {
-		sep = (CTR_read() & CTR_SEP_FLAG) == CTR_SEP_FLAG;
-	} else {
-		printf("Unknown cache type.\n");
-		halt();
-	}
-#endif
-
-	for (uintptr_t a = ALIGN_DOWN(addr, CP15_C7_MVA_ALIGN); a < addr + size;
-	    a += CP15_C7_MVA_ALIGN) {
-#if defined(PROCESSOR_ARCH_armv7_a)
-		DCCMVAC_write(a);
-#else
-		if (sep)
-			DCCMVA_write(a);
-		else
-			CCMVA_write(a);
-#endif
+	const uintptr_t addr = (uintptr_t)address;
+	for (uintptr_t a = addr; a < addr + size; a += 4) {
+		/* DCCMVAC - clean by address to the point of coherence */
+		asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : );
 	}
 }
Index: boot/arch/arm32/src/mm.c
===================================================================
--- boot/arch/arm32/src/mm.c	(revision 5265eea4b6e13925ae465dd16a7d61a8c7dd994d)
+++ boot/arch/arm32/src/mm.c	(revision 03289871c675b83ed939beb60680fb3245e1eea6)
@@ -143,5 +143,5 @@
 	pte->should_be_zero_1 = 0;
 	pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW;
-#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
+#ifdef PROCESSOR_ARCH_armv7_a
 	/*
 	 * Keeps this setting in sync with memory type attributes in:
@@ -152,7 +152,7 @@
 	pte->tex = section_cacheable(frame) ? 5 : 0;
 	pte->cacheable = section_cacheable(frame) ? 0 : 0;
-	pte->bufferable = section_cacheable(frame) ? 1 : 1;
+	pte->bufferable = section_cacheable(frame) ? 1 : 0;
 #else
-	pte->bufferable = section_cacheable(frame);
+	pte->bufferable = 1;
 	pte->cacheable = section_cacheable(frame);
 	pte->tex = 0;
@@ -189,8 +189,5 @@
 	 */
 	uint32_t val = (uint32_t)boot_pt & TTBR_ADDR_MASK;
-#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
-	// FIXME: TTBR_RGN_WBWA_CACHE is unpredictable on ARMv6
 	val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG;
-#endif
 	TTBR0_write(val);
 }
Index: kernel/arch/arm32/include/arch/atomic.h
===================================================================
--- kernel/arch/arm32/include/arch/atomic.h	(revision 5265eea4b6e13925ae465dd16a7d61a8c7dd994d)
+++ kernel/arch/arm32/include/arch/atomic.h	(revision 03289871c675b83ed939beb60680fb3245e1eea6)
@@ -78,6 +78,5 @@
  *
  */
-NO_TRACE static inline void atomic_dec(atomic_t *val)
-{
+NO_TRACE static inline void atomic_dec(atomic_t *val) {
 	atomic_add(val, -1);
 }
Index: kernel/arch/arm32/include/arch/barrier.h
===================================================================
--- kernel/arch/arm32/include/arch/barrier.h	(revision 5265eea4b6e13925ae465dd16a7d61a8c7dd994d)
+++ kernel/arch/arm32/include/arch/barrier.h	(revision 03289871c675b83ed939beb60680fb3245e1eea6)
@@ -38,7 +38,5 @@
 
 #ifdef KERNEL
-#include <arch/cache.h>
 #include <arch/cp15.h>
-#include <align.h>
 #else
 #include <libarch/cp15.h>
@@ -73,16 +71,8 @@
  * CP15 implementation is mandatory only for armv6+.
  */
-#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 #define memory_barrier()  CP15DMB_write(0)
-#else
-#define memory_barrier()  CP15DSB_write(0)
-#endif
-#define read_barrier()    CP15DSB_write(0) 
+#define read_barrier()    CP15DSB_write(0)
 #define write_barrier()   read_barrier()
-#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 #define inst_barrier()    CP15ISB_write(0)
-#else
-#define inst_barrier()
-#endif
 #else
 /* Older manuals mention syscalls as a way to implement cache coherency and
@@ -113,10 +103,12 @@
 
 #if defined PROCESSOR_ARCH_armv7_a | defined PROCESSOR_ARCH_armv6 | defined KERNEL
+/* Available on all supported arms,
+ * invalidates entire ICache so the written value does not matter. */
 //TODO might be PL1 only on armv5-
 #define smc_coherence(a) \
 do { \
-	dcache_clean_mva_pou(ALIGN_DOWN((uintptr_t) a, CP15_C7_MVA_ALIGN)); \
+	DCCMVAU_write((uint32_t)(a));  /* Flush changed memory */\
 	write_barrier();               /* Wait for completion */\
-	icache_invalidate();\
+	ICIALLU_write(0);              /* Flush ICache */\
 	inst_barrier();                /* Wait for Inst refetch */\
 } while (0)
@@ -125,6 +117,5 @@
 #define smc_coherence_block(a, l) \
 do { \
-	for (uintptr_t addr = (uintptr_t) a; addr < (uintptr_t) a + l; \
-	    addr += CP15_C7_MVA_ALIGN) \
+	for (uintptr_t addr = (uintptr_t)a; addr < (uintptr_t)a + l; addr += 4)\
 		smc_coherence(addr); \
 } while (0)
Index: kernel/arch/arm32/include/arch/cache.h
===================================================================
--- kernel/arch/arm32/include/arch/cache.h	(revision 5265eea4b6e13925ae465dd16a7d61a8c7dd994d)
+++ kernel/arch/arm32/include/arch/cache.h	(revision 03289871c675b83ed939beb60680fb3245e1eea6)
@@ -37,6 +37,4 @@
 #define KERN_arm32_CACHE_H_
 
-#include <typedefs.h>
-
 unsigned dcache_levels(void);
 
@@ -45,7 +43,5 @@
 void cpu_dcache_flush(void);
 void cpu_dcache_flush_invalidate(void);
-extern void icache_invalidate(void);
-extern void dcache_invalidate(void);
-extern void dcache_clean_mva_pou(uintptr_t);
+void icache_invalidate(void);
 
 #endif
Index: kernel/arch/arm32/include/arch/cp15.h
===================================================================
--- kernel/arch/arm32/include/arch/cp15.h	(revision 5265eea4b6e13925ae465dd16a7d61a8c7dd994d)
+++ kernel/arch/arm32/include/arch/cp15.h	(revision 03289871c675b83ed939beb60680fb3245e1eea6)
@@ -118,19 +118,8 @@
 };
 CONTROL_REG_GEN_READ(CTR, c0, 0, c0, 1);
-
-#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_READ(TCMR, c0, 0, c0, 2);
-
-enum {
-	TLBTR_SEP_FLAG = 1,
-};
-
 CONTROL_REG_GEN_READ(TLBTR, c0, 0, c0, 3);
-#endif
-
-#if defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_READ(MPIDR, c0, 0, c0, 5);
 CONTROL_REG_GEN_READ(REVIDR, c0, 0, c0, 6);
-#endif
 
 enum {
@@ -320,5 +309,4 @@
 enum {
 	TTBR_ADDR_MASK = 0xffffff80,
-#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 	TTBR_NOS_FLAG = 1 << 5,
 	TTBR_RGN_MASK = 0x3 << 3,
@@ -329,17 +317,12 @@
 	TTBR_S_FLAG = 1 << 1,
 	TTBR_C_FLAG = 1 << 0,
-#endif
 };
 CONTROL_REG_GEN_READ(TTBR0, c2, 0, c0, 0);
 CONTROL_REG_GEN_WRITE(TTBR0, c2, 0, c0, 0);
-
-#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_READ(TTBR1, c2, 0, c0, 1);
 CONTROL_REG_GEN_WRITE(TTBR1, c2, 0, c0, 1);
 CONTROL_REG_GEN_READ(TTBCR, c2, 0, c0, 2);
 CONTROL_REG_GEN_WRITE(TTBCR, c2, 0, c0, 2);
-#endif
-
-#if defined(PROCESSOR_ARCH_armv7)
+
 CONTROL_REG_GEN_READ(HTCR, c2, 4, c0, 2);
 CONTROL_REG_GEN_WRITE(HTCR, c2, 4, c0, 2);
@@ -356,5 +339,4 @@
 CONTROL_REG_GEN_READ(VTTBRH, c2, 0, c2, 6);
 CONTROL_REG_GEN_WRITE(VTTBRH, c2, 0, c2, 6);
-#endif
 
 CONTROL_REG_GEN_READ(DACR, c3, 0, c0, 0);
@@ -391,167 +373,71 @@
 CONTROL_REG_GEN_WRITE(HPFAR, c6, 4, c0, 4);
 
-/*
- * Cache maintenance, address translation and other
- */
-
-#if defined(PROCESSOR_cortex_a8)
-#define CP15_C7_MVA_ALIGN	64
-#elif defined(PROCESSOR_arm1176)
-#define CP15_C7_MVA_ALIGN	32
-#elif defined(PROCESSOR_arm926ej_s)
-#define CP15_C7_MVA_ALIGN	32
-#elif defined(PROCESSOR_arm920t)
-#define CP15_C7_MVA_ALIGN	32
-#else
-#error Unknow MVA alignment
-#endif
-
-#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
+/* Cache maintenance, address translation and other */
+CONTROL_REG_GEN_WRITE(WFI, c7, 0, c0, 4); /* armv6 only */
+CONTROL_REG_GEN_WRITE(ICIALLLUIS, c7, 0, c1, 0);
+CONTROL_REG_GEN_WRITE(BPIALLIS, c7, 0, c1, 6);
+CONTROL_REG_GEN_READ(PAR, c7, 0, c4, 0);
+CONTROL_REG_GEN_WRITE(PAR, c7, 0, c4, 0);
+CONTROL_REG_GEN_READ(PARH, c7, 0, c7, 0);   /* PAE */
+CONTROL_REG_GEN_WRITE(PARH, c7, 0, c7, 0);   /* PAE */
+CONTROL_REG_GEN_WRITE(ICIALLU, c7, 0, c5, 0);
+CONTROL_REG_GEN_WRITE(ICIMVAU, c7, 0, c5, 1);
 CONTROL_REG_GEN_WRITE(CP15ISB, c7, 0, c5, 4);
 CONTROL_REG_GEN_WRITE(BPIALL, c7, 0, c5, 6);
 CONTROL_REG_GEN_WRITE(BPIMVA, c7, 0, c5, 7);
-#endif
-
-#if !defined(PROCESSOR_arm920t)
+
+CONTROL_REG_GEN_WRITE(DCIMVAC, c7, 0, c6, 1);
 CONTROL_REG_GEN_WRITE(DCISW, c7, 0, c6, 2);
-#endif
-
-#if defined(PROCESSOR_arm920t) || !defined(PROCESSOR_ARCH_armv4)
+
+CONTROL_REG_GEN_WRITE(ATS1CPR, c7, 0, c8, 0);
+CONTROL_REG_GEN_WRITE(ATS1CPW, c7, 0, c8, 1);
+CONTROL_REG_GEN_WRITE(ATS1CUR, c7, 0, c8, 2);
+CONTROL_REG_GEN_WRITE(ATS1CUW, c7, 0, c8, 3);
+CONTROL_REG_GEN_WRITE(ATS12NSOPR, c7, 0, c8, 4);
+CONTROL_REG_GEN_WRITE(ATS12NSOPW, c7, 0, c8, 5);
+CONTROL_REG_GEN_WRITE(ATS12NSOUR, c7, 0, c8, 6);
+CONTROL_REG_GEN_WRITE(ATS12NSOUW, c7, 0, c8, 7);
+
+
+CONTROL_REG_GEN_WRITE(DCCMVAC, c7, 0, c10, 1);
 CONTROL_REG_GEN_WRITE(DCCSW, c7, 0, c10, 2);
-#endif
-
 CONTROL_REG_GEN_WRITE(CP15DSB, c7, 0, c10, 4);
-
-#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_WRITE(CP15DMB, c7, 0, c10, 5);
-#endif
-
-#if defined(PROCESSOR_arm920t) || !defined(PROCESSOR_ARCH_armv4)
+CONTROL_REG_GEN_WRITE(DCCMVAU, c7, 0, c11, 1);
+
+CONTROL_REG_GEN_WRITE(PFI, c7, 0, c11, 1); /* armv6 only */
+
+CONTROL_REG_GEN_WRITE(DCCIMVAC, c7, 0, c14, 1);
 CONTROL_REG_GEN_WRITE(DCCISW, c7, 0, c14, 2);
-#endif
-
-#if defined(PROCESSOR_ARCH_armv7_a)
-CONTROL_REG_GEN_WRITE(ICIALLLUIS, c7, 0, c1, 0);
-CONTROL_REG_GEN_WRITE(BPIALLIS, c7, 0, c1, 6);
-CONTROL_REG_GEN_READ(PAR, c7, 0, c4, 0); /* Security Extensions */
-CONTROL_REG_GEN_WRITE(PAR, c7, 0, c4, 0); /* Security Extensions */
-CONTROL_REG_GEN_WRITE(ICIALLU, c7, 0, c5, 0);
-CONTROL_REG_GEN_WRITE(ICIMVAU, c7, 0, c5, 1);
-CONTROL_REG_GEN_WRITE(DCIMVAC, c7, 0, c6, 1);
-CONTROL_REG_GEN_READ(PARH, c7, 0, c7, 0); /* PAE */
-CONTROL_REG_GEN_WRITE(PARH, c7, 0, c7, 0); /* PAE */
-CONTROL_REG_GEN_WRITE(ATS1CPR, c7, 0, c8, 0); /* Security Extensions */
-CONTROL_REG_GEN_WRITE(ATS1CPW, c7, 0, c8, 1); /* Security Extensions */
-CONTROL_REG_GEN_WRITE(ATS1CUR, c7, 0, c8, 2); /* Security Extensions */
-CONTROL_REG_GEN_WRITE(ATS1CUW, c7, 0, c8, 3); /* Security Extensions */
-CONTROL_REG_GEN_WRITE(ATS12NSOPR, c7, 0, c8, 4); /* Security Extensions */
-CONTROL_REG_GEN_WRITE(ATS12NSOPW, c7, 0, c8, 5); /* Security Extensions */
-CONTROL_REG_GEN_WRITE(ATS12NSOUR, c7, 0, c8, 6); /* Security Extensions */
-CONTROL_REG_GEN_WRITE(ATS12NSOUW, c7, 0, c8, 7); /* Security Extensions */
-CONTROL_REG_GEN_WRITE(ATS1HR, c7, 4, c8, 0); /* Virtualization Extensions */
-CONTROL_REG_GEN_WRITE(ATS1HW, c7, 4, c8, 1); /* Virtualization Extensions */
-CONTROL_REG_GEN_WRITE(DCCMVAC, c7, 0, c10, 1);
-CONTROL_REG_GEN_WRITE(DCCMVAU, c7, 0, c11, 1);
-CONTROL_REG_GEN_WRITE(DCCIMVAC, c7, 0, c14, 1);
-#else
-
-#if defined(PROCESSOR_arm920t) || !defined(PROCESSOR_ARCH_armv4)
-CONTROL_REG_GEN_WRITE(WFI, c7, 0, c0, 4);
-#endif
-
-CONTROL_REG_GEN_WRITE(ICIALL, c7, 0, c5, 0);
-CONTROL_REG_GEN_WRITE(ICIMVA, c7, 0, c5, 1);
-
-#if !defined(PROCESSOR_ARCH_armv4)
-CONTROL_REG_GEN_WRITE(ICISW, c7, 0, c5, 2);
-#endif
-
-CONTROL_REG_GEN_WRITE(DCIALL, c7, 0, c6, 0);
-CONTROL_REG_GEN_WRITE(DCIMVA, c7, 0, c6, 1);
-CONTROL_REG_GEN_WRITE(CIALL, c7, 0, c7, 0);
-CONTROL_REG_GEN_WRITE(CIMVA, c7, 0, c7, 1);
-
-#if !defined(PROCESSOR_ARCH_armv4)
-CONTROL_REG_GEN_WRITE(CISW, c7, 0, c7, 2);
-#endif
-
-#if defined(PROCESSOR_ARCH_armv4) || defined(PROCESSOR_ARCH_armv6)
-CONTROL_REG_GEN_WRITE(DCCALL, c7, 0, c10, 0);
-#endif
-
-CONTROL_REG_GEN_WRITE(DCCMVA, c7, 0, c10, 1);
-
-#if defined(PROCESSOR_ARCH_armv4) || defined(PROCESSOR_ARCH_armv6)
-CONTROL_REG_GEN_WRITE(CCALL, c7, 0, c11, 0);
-#endif
-
-CONTROL_REG_GEN_WRITE(CCMVA, c7, 0, c11, 1);
-
-#if !defined(PROCESSOR_ARCH_armv4)
-CONTROL_REG_GEN_WRITE(CCSW, c7, 0, c11, 2);
-#endif
-
-#if defined(PROCESSOR_arm920t) || !defined(PROCESSOR_ARCH_armv4)
-CONTROL_REG_GEN_WRITE(PFIMVA, c7, 0, c13, 1);
-#endif
-
-#if defined(PROCESSOR_ARCH_armv4) || defined(PROCESSOR_ARCH_armv6)
-CONTROL_REG_GEN_WRITE(DCCIALL, c7, 0, c14, 0);
-#endif
-
-CONTROL_REG_GEN_WRITE(DCCIMVA, c7, 0, c14, 1);
-
-#if defined(PROCESSOR_ARCH_armv4) || defined(PROCESSOR_ARCH_armv6)
-CONTROL_REG_GEN_WRITE(CCIALL, c7, 0, c15, 0);
-#endif
-
-CONTROL_REG_GEN_WRITE(CCIMVA, c7, 0, c15, 1);
-
-#if defined(PROCESSOR_ARCH_armv5) || defined(PROCESSOR_ARCH_armv6)
-CONTROL_REG_GEN_WRITE(CCISW, c7, 0, c15, 2);
-#endif
-
-#endif
+
+CONTROL_REG_GEN_WRITE(ATS1HR, c7, 4, c8, 0);
+CONTROL_REG_GEN_WRITE(ATS1HW, c7, 4, c8, 1);
 
 /* TLB maintenance */
-#if defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_WRITE(TLBIALLIS, c8, 0, c3, 0); /* Inner shareable */
 CONTROL_REG_GEN_WRITE(TLBIMVAIS, c8, 0, c3, 1); /* Inner shareable */
 CONTROL_REG_GEN_WRITE(TLBIASIDIS, c8, 0, c3, 2); /* Inner shareable */
 CONTROL_REG_GEN_WRITE(TLBIMVAAIS, c8, 0, c3, 3); /* Inner shareable */
-#endif
 
 CONTROL_REG_GEN_WRITE(ITLBIALL, c8, 0, c5, 0);
 CONTROL_REG_GEN_WRITE(ITLBIMVA, c8, 0, c5, 1);
-#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_WRITE(ITLBIASID, c8, 0, c5, 2);
-#endif
 
 CONTROL_REG_GEN_WRITE(DTLBIALL, c8, 0, c6, 0);
 CONTROL_REG_GEN_WRITE(DTLBIMVA, c8, 0, c6, 1);
-#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_WRITE(DTLBIASID, c8, 0, c6, 2);
-#endif
 
 CONTROL_REG_GEN_WRITE(TLBIALL, c8, 0, c7, 0);
 CONTROL_REG_GEN_WRITE(TLBIMVA, c8, 0, c7, 1);
-#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_WRITE(TLBIASID, c8, 0, c7, 2);
-#endif
-#if defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_WRITE(TLBIMVAA, c8, 0, c7, 3);
-#endif
-
-#if defined(PROCESSOR_ARCH_armv7_a)
+
 CONTROL_REG_GEN_WRITE(TLBIALLHIS, c8, 4, c3, 0); /* Inner shareable */
 CONTROL_REG_GEN_WRITE(TLBIMVAHIS, c8, 4, c3, 1); /* Inner shareable */
 CONTROL_REG_GEN_WRITE(TLBIALLNSNHIS, c8, 4, c3, 4); /* Inner shareable */
-#endif
-
-#if defined(PROCESSOR_ARCH_armv7_a)
+
 CONTROL_REG_GEN_WRITE(TLBIALLH, c8, 4, c7, 0);
 CONTROL_REG_GEN_WRITE(TLBIMVAH, c8, 4, c7, 1);
 CONTROL_REG_GEN_WRITE(TLBIALLNSNHS, c8, 4, c7, 4);
-#endif
 
 /* c9 are performance monitoring resgisters */
Index: kernel/arch/arm32/include/arch/mm/page.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page.h	(revision 5265eea4b6e13925ae465dd16a7d61a8c7dd994d)
+++ kernel/arch/arm32/include/arch/mm/page.h	(revision 03289871c675b83ed939beb60680fb3245e1eea6)
@@ -154,8 +154,5 @@
 {
 	uint32_t val = (uint32_t)pt & TTBR_ADDR_MASK;
-#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
-	// FIXME: TTBR_RGN_WBWA_CACHE is unpredictable on ARMv6
 	val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG;
-#endif
 	TTBR0_write(val);
 }
Index: kernel/arch/arm32/include/arch/mm/page_armv4.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page_armv4.h	(revision 5265eea4b6e13925ae465dd16a7d61a8c7dd994d)
+++ kernel/arch/arm32/include/arch/mm/page_armv4.h	(revision 03289871c675b83ed939beb60680fb3245e1eea6)
@@ -123,5 +123,5 @@
 do { \
 	for (unsigned i = 0; i < count; ++i) \
-		dcache_clean_mva_pou((uintptr_t)(pt + i)); \
+		DCCMVAU_write((uintptr_t)(pt + i)); \
 	read_barrier(); \
 } while (0)
Index: kernel/arch/arm32/include/arch/mm/page_armv6.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page_armv6.h	(revision 5265eea4b6e13925ae465dd16a7d61a8c7dd994d)
+++ kernel/arch/arm32/include/arch/mm/page_armv6.h	(revision 03289871c675b83ed939beb60680fb3245e1eea6)
@@ -156,7 +156,8 @@
 do { \
 	for (unsigned i = 0; i < count; ++i) \
-		dcache_clean_mva_pou((uintptr_t)(pt + i)); \
+		DCCMVAU_write((uintptr_t)(pt + i)); \
 	read_barrier(); \
 } while (0)
+
 
 /** Returns level 0 page table entry flags.
@@ -257,8 +258,6 @@
 	if (flags & PAGE_CACHEABLE) {
 		/*
-		 * Outer and inner write-back, write-allocate memory,
-		 * see ch. B3.8.2 (p. B3-1358) of ARM Architecture reference
-		 * manual.
-		 *
+		 * Write-through, write-allocate memory, see ch. B3.8.2
+		 * (p. B3-1358) of ARM Architecture reference manual.
 		 * Make sure the memory type is correct, and in sync with:
 		 * init_boot_pt (boot/arch/arm32/src/mm.c)
@@ -279,7 +278,12 @@
 	}
 	
+#if defined(PROCESSOR_ARCH_armv6)
+	/* FIXME: this disables caches */
+	p->shareable = 1;
+#else
 	/* Shareable is ignored for devices (non-cacheable),
 	 * turn it off for normal memory. */
 	p->shareable = 0;
+#endif
 	
 	p->non_global = !(flags & PAGE_GLOBAL);
Index: kernel/arch/arm32/src/cpu/cpu.c
===================================================================
--- kernel/arch/arm32/src/cpu/cpu.c	(revision 5265eea4b6e13925ae465dd16a7d61a8c7dd994d)
+++ kernel/arch/arm32/src/cpu/cpu.c	(revision 03289871c675b83ed939beb60680fb3245e1eea6)
@@ -130,8 +130,5 @@
 {
 	uint32_t control_reg = SCTLR_read();
-
-	dcache_invalidate();
-	read_barrier();
-
+	
 	/* Turn off tex remap, RAZ/WI prior to armv7 */
 	control_reg &= ~SCTLR_TEX_REMAP_EN_FLAG;
@@ -325,45 +322,5 @@
 void icache_invalidate(void)
 {
-#if defined(PROCESSOR_ARCH_armv7_a)
 	ICIALLU_write(0);
-#else
-	ICIALL_write(0);
-#endif
-}
-
-#if !defined(PROCESSOR_ARCH_armv7_a)
-static bool cache_is_unified(void)
-{
-	if (MIDR_read() != CTR_read()) {
-		/* We have the CTR register */
-		return (CTR_read() & CTR_SEP_FLAG) != CTR_SEP_FLAG;
-	} else {
-		panic("Unknown cache type");
-	}
-}
-#endif
-
-void dcache_invalidate(void)
-{
-#if defined(PROCESSOR_ARCH_armv7_a)
-	dcache_flush_invalidate();
-#else
-	if (cache_is_unified())
-		CIALL_write(0);
-	else
-		DCIALL_write(0);
-#endif
-}
-
-void dcache_clean_mva_pou(uintptr_t mva)
-{
-#if defined(PROCESSOR_ARCH_armv7_a)
-	DCCMVAU_write(mva);
-#else
-	if (cache_is_unified())
-		CCMVA_write(mva);
-	else
-		DCCMVA_write(mva);
-#endif
 }
 
Index: kernel/arch/arm32/src/mm/tlb.c
===================================================================
--- kernel/arch/arm32/src/mm/tlb.c	(revision 5265eea4b6e13925ae465dd16a7d61a8c7dd994d)
+++ kernel/arch/arm32/src/mm/tlb.c	(revision 03289871c675b83ed939beb60680fb3245e1eea6)
@@ -79,20 +79,6 @@
 static inline void invalidate_page(uintptr_t page)
 {
-#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
-	if (TLBTR_read() & TLBTR_SEP_FLAG) {
-		ITLBIMVA_write(page);
-		DTLBIMVA_write(page);
-	} else {
-		TLBIMVA_write(page);
-	}
-#elif defined(PROCESSOR_arm920t)
-	ITLBIMVA_write(page);
-	DTLBIMVA_write(page);
-#elif defined(PROCESSOR_arm926ej_s)
+	//TODO: What about TLBIMVAA?
 	TLBIMVA_write(page);
-#else
-#error Unknown TLB type
-#endif
-
 	/*
 	 * "A TLB maintenance operation is only guaranteed to be complete after
